The invention relates to the field of data processing in communications networks and more specifically to a method and circuit for detecting standard patterns in data such as those found in header bytes SONET-based telecommunication systems.
In some telecommunication systems, data is transmitted with a predetermined structure called the frame. The frame typically contains a header (or overhead) section where information about the particular frame resides, and a payload section where the actual data resides. Different data transmission protocols may required different data frame. For example, SONET (Synchronous Optical Network) which is a transmission multiplexing standard for high-speed data communications within North America, has as its basic building block a 51.84 Mb/s, OC-1 (Optical Carrier 1) frame. The organization of an OC-1 frame 24 is depicted in FIG. 7. The structure of the OC-1 frame 24 can be thought of as a two dimensional matrix having nine rows 25 with each row 25 containing 90 bytes of data. The frame's data is transmitted row by row, from left to right with the most significant bit (MSB) of each byte being transmitted first. The first three columns of each frame form the header section that is divided between section overhead 26 and line overhead 27 as shown. The remainder of the frame carries the synchronous payload envelope (SPE) 28 containing the data. The section overhead 26 includes a series of named bytes. Two of the named bytes, A1 and A2 signal the start of the OC-1 frame. According to the SONET standard, the A1 byte has a value F6 in hexadecimal (1111—0110 in binary) and the A2 byte has a value of 28 (0010—1000 in binary).
To achieve high data rates, multiple frame-aligned OC-1 signals are multiplexed to form a higher frequency OC-N signal. FIG. 7 shows an OC-N signal 23 which is made up of N OC-1 frames (24, 24a, 24b, etc.). The OC-N signal 23 allows the system to operate at a frequency of (N)×(51.84 Mb/s). As shown in FIG. 7, the OC-N signal 23 can be viewed as a three dimensional frame having a depth of N tiers, each of which is an OC-1 frame 24. In SONET, data is transmitted serially with the sequence of byte transmission indexed first by tier depth N then by row then by column. So the A1 byte of OC-1 frame 24 would be transmitted first, followed by the A1 byte of OC-1 frame 24a, followed by the A1 byte of OC-1 frame 24b, etc. After the A1 bytes of all N OC-1 frames are transmitted, the sequence steps along the row, and the A2 bytes of the OC-1 frames, 24, 24a, 24b, etc. are transmitted. The beginning pattern for an OC-N SONET signal is thus N consecutive A1 bytes (A1=F6) followed by N consecutive A2 bytes (A2=28). This distinctive sequence must be detected by a SONET receiver in order to distinguish the start of an OC-N frame.
At the receiver end, the serial SONET data is first deserialized from a serial bitstream onto a multiple-bit (e.g., 16 bit) wide parallel data bus by a SERDES (Serializer/Deserializer) chip. The 16 bit wide bus is then further deserialized into a 128-bit wide parallel bus for data processing in an OC-N framer chip. Since data arrives from the optical fiber as a serial bitstream, the data on the 128 bit bus, after the two deserializing steps, may not fall on the A1A2 boundary. A method is needed to rearrange the data and align it in such a way that the data aligns along the A1A2 boundary.
Several methods of accomplishing this data alignment are known in the art. For example, one known method compares the 128 bits of data on the data bus with A1 and A2 directly. As the A1A2 boundary can fall on any of the 128 bits, detecting the A1A2 boundary in one clock cycle according to this method requires 128, 128-bit comparators. The circuitry needed to accomplish detection of the A1A2 boundary according to this method is too large to be commercially practicable. Assuming state of the art 0.18 micron process technology, a single 128 bit comparator has about 4,500 unit cells. Implementation of 128 such comparators would thus require 756,000 unit cells. Realignment by this method would also require 128, 128-to-1 multiplexers, each of which requires 3,000 unit cells to implement. The total unit cell cost of the known direct comparison method is 1,100,000 unit cells, which is quite expensive.
An alternative method requires only one 128-bit comparator which directly compares the 128-bit data bus with A1 and A2. In order to cover all possible locations of the A1A2 boundary, this second method shifts the 128-bit register one bit between every comparison until the boundary is found. This method has the advantage of requiring much less circuitry to implement, but requires potentially 128 clock cycles to detect the A1A2 boundary. Such a long delay is not acceptable in real time data processing.
A third method for detecting the A1A2 boundary moves the detection logic one level closer to the line level. If detection can be performed at the input to the OC-N framer, on a 16-bit wide bus, unit cell savings can be realized. The shortcoming with this method is that the comparison has to be made at a much higher clock frequency (622 MHz), which is a difficult timing requirement to meet.
What is needed is a method and circuitry for detecting data patterns such as the A1A2 boundary in an OC-N SONET frame using a small number of clock cycles and minimal circuit overhead.